The present disclosure relates to a PLL circuit, an error correcting method for the same, and a communication apparatus including the same.
For the purpose of locking a carrier frequency to a precise frequency, a Phase Locked Loop (PLL) circuit is used in a wireless communication terminal. In recent years, along with the scale down of the semiconductor process, attention is being focused on a configuration in which a Voltage Controlled Oscillator (VCO) adapted to be controlled with an analog voltage is replaced with a Digital Controlled Oscillator (DCO).
In the existing PLL circuit using the VCO, a phase comparator compares a phase difference between a reference clock and clock obtained by frequency-dividing a VCO output signal with each other. Here, a circuit for converting a phase difference into a pulse width taking three states: up; down; and up+down is used as the general phase comparator. Also, a current source of a charge pump circuit is controlled by using this pulse, and a current outputted is converted into a voltage by a loop filter, thereby controlling the VCO.
On the other hand, FIG. 11 shows an example of an All-Digital PLL circuit using the DCO on which attention has been focused recently. In the All-Digital PLL circuit using the DCO, a Fractional component of the number of accumulated clocks corresponding to a phase difference is converted into a digital value by a Time-to-Digital Converter (TDC) circuit, and an Integer component thereof is converted into a digital value by an accumulator circuit. Also, a digital value corresponding to a phase difference between these digital values thus detected is fed back by utilizing any of various methods, thereby digitally controlling the DCO. Such a technique, for example, is disclosed in a related-art document of R. B. Staszewski et al. “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13 μm CMOS, ISSCC2004 Digest.